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SN54/74LS299 8-BIT SHIFT/STORAGE REGISTER WITH 3-STATE OUTPUTS
The SN54 / 74LS299 is an 8-Bit Universal Shift / Storage Register with 3-state outputs. Four modes of operation are possible: hold (store), shift left, shift right and load data. The parallel load inputs and flip-flop outputs are multiplexed to reduce the total number of package pins. Separate outputs are provided for flip-flops Q0 and Q7 to allow easy cascading. A separate active LOW Master Reset is used to reset the register.
8-BIT SHIFT/STORAGE REGISTER WITH 3-STATE OUTPUTS
LOW POWER SCHOTTKY
* Common I/O for Reduced Pin Count * Four Operation Modes: Shift Left, Shift Right, Load and Store * Separate Shift Right Serial Input and Shift Left Serial Input for Easy
Cascading * 3-State Outputs for Bus Oriented Applications * Input Clamp Diodes Limit High-Speed Termination Effects * ESD > 3500 Volts
20 1
J SUFFIX CERAMIC CASE 732-03
20
N SUFFIX PLASTIC CASE 738-03
1
CONNECTION DIAGRAM DIP (TOP VIEW)
VCC S1 20 19 Ds7 18 Q7 17 I/O7 I/O5 I/O3 I/O1 CP 16 15 14 13 12 DS0 11
20 NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package. 1
DW SUFFIX SOIC CASE 751D-03
ORDERING INFORMATION
SN54LSXXXJ Ceramic SN74LSXXXN Plastic SN74LSXXXDW SOIC
1 S0
2 3 4 5 6 8 7 OE1 OE2 I/O6 I/O4 I/O2 I/O0 Q0
9 10 MR GND
PIN NAMES HIGH CP DS0 DS7 I/On OE1, OE2 Q0, Q7 MR S0, S1 Clock Pulse (active positive-going edge) Input Serial Data Input for Right Shift Serial Data Input for Left Shift Parallel Data Input or Parallel Output (3-State) (Note c) 3-State Output Enable (active LOW) Inputs Serial Outputs (Note b) Asynchronous Master Reset (active LOW) Input Mode Select Inputs
LOADING (Note a) LOW 0.25 U.L. 0.25 U.L. 0.25 U.L. 0.25 U.L. 15 (7.5) U.L. 0.25 U.L. 5 (2.5) U.L. 0.25 U.L. 0.5 U.L.
0.5 U.L. 0.5 U.L. 0.5 U.L. 0.5 U.L. 65 (25) U.L. 0.5 U.L. 10 U.L. 0.5 U.L. 1 U.L.
NOTES: a) 1 TTL Unit Load (U.L.) = 40 A HIGH/1.6 mA LOW. b) The Output LOW drive factor is 2.5 U.L for Military (54) and 5 U.L. for Commercial (74) Temperature Ranges. c) The Output LOW drive factor is 7.5 U.L for Military (54) and 15 U.L. for Commercial (74). The Output HIGH drive factor is 25 U.L. for Military (54) and 65 U.L. for Commercial (74) Temperature Ranges.
FAST AND LS TTL DATA 5-1
SN54/74LS299
LOGIC DIAGRAM
S1 19 S0
1
18
DS7 DS0
11
12
CLOCK Q0 MR OE1 OE2
8 9 2 3
D CK CLR Q
D CK CLR Q
D CK CLR Q
D CK CLR Q
D CK CLR Q
D CK CLR Q
D CK CLR Q
D CK CLR Q
17
Q7 VCC = PIN 20 GND = PIN 10 = PIN NUMBERS
7
13
6
14
5
15
4
16
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
FUNCTION TABLE
INPUTS MR L L L L L H H H H H H H H S1 X X H L X L L H H H L L L S0 X X H X L H H L L H L L L OE1 H X X L L X L X L X H X L OE2 X H X L L X L X L X X H L X X X CP X X X X X DS0 X X X X X D D X X X X X X DS7 X X X X X X X D D X X X X Asynchronous Reset; Q0 = Q7 = LOW I/O Voltage Undetermined Asynchronous Reset; Q 0 = Q7 = LOW I/O Voltage LOW Shift Right; DQ0; Q0Q1; etc. Shift Right; DQ0 & I/O0; Q0O1 & I/O1; etc. Shift Left; DQ7; Q7Q6; etc. Shift Left; DQ7 & I/O7; Q7Q6 & I/O6; etc. Parallel Load; I/OnQn Hold: I/O Voltage undetermined Hold: I/On = Qn RESPONSE
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial
GUARANTEED OPERATING RANGES
Symbol VCC TA IOH IOL IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current -- High Output Current -- Low Output Current -- High Output Current -- Low Q0, Q7 Q0, Q7 Q0, Q7 I/O0 - I/O7 I/O0 - I/O7 I/O0 - I/O7 I/O0 - I/O7 Parameter 54 74 54 74 54, 74 54 74 54 74 54 74 Min 4.5 4.75 - 55 0 Typ 5.0 5.0 25 25 Max 5.5 5.25 125 70 - 0.4 4.0 8.0 - 1.0 - 2.6 12 24 Unit V C mA mA mA mA
FAST AND LS TTL DATA 5-2
SN54/74LS299
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits Symbol S bl VIH VIL VIK VOH Parameter P Input HIGH Voltage 54 Input LOW Voltage 74 Input Clamp Diode Voltage Output HIGH Voltage p g I/O0 - I/O7 Output HIGH Voltage p g Q0, Q7 Output LOW Voltage p g I/O0 - I/O7 Output LOW Voltage p g I/O0 - I/O7 Output Off Current HIGH I/O0 - I/O7 Output Off Current LOW I/O0 - I/O7 Others S0, S1, I/O0 - I/O7 IIH Input HIGH C I Current Others S0, S1 I/O0 - I/O7 Others IIL IOS Input LOW Current S0, S1 Short Circuit Current (Note 1) Power Supply Current Q0, Q7 I/O0 - I/O7 - 20 - 30 - 0.8 -100 -130 53 mA mA mA mA 54 74 54 74 54, 74 74 54, 74 74 2.4 2.4 2.5 2.7 - 0.65 3.2 3.1 3.4 3.4 0.25 0.35 0.4 0.5 0.4 0.5 40 - 400 20 40 0.1 0.2 0.1 - 0.4 0.8 - 1.5 V V V V V V V V V A A A A mA mA mA mA VCC = MAX VIN = 0 4 V MAX, 0.4 VCC = MAX VCC = MAX VCC = MAX VCC = MAX VIN = 7 0 V MAX, 7.0 VCC = MAX, VIN = 5.5 V VCC = MAX VIN = 2.7 V MAX, 27 VCC = MIN IOH = MAX MIN, IOL = 12 mA IOL = 24 mA IOL = 4.0 mA IOL = 8.0 mA VCC = VCC MIN, VIN = VIL or VIH per Truth Table VCC = VCC MIN, VIN = VIL or VIH per Truth Table VCC = MIN IOH = MAX MIN, Min 2.0 0.7 V Typ Max Unit Ui V Test C di i T Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for p g All Inputs VCC = MIN, IIN = - 18 mA
VOH
VOL
VOL IOZH IOZL
VCC = MAX, VOUT = 2.7 V VCC = MAX, VOUT = 0.4 V
ICC
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
FAST AND LS TTL DATA 5-3
SN54/74LS299
AC CHARACTERISTICS (TA = 25C, VCC = 5.0 V)
Limits Symbol S bl fMAX tPHL tPLH tPHL tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ Parameter P Maximum Clock Frequency Propagation Delay, Clock to Q0 or Q7 Propagation Delay, Clear to Q0 or Q7 Propagation Delay, Clock to I/O0 - I/O7 Propagation Delay, Clear to I/O0 - I/O7 Output Enable Time Output Disable Time Min 25 Typ 35 26 22 27 26 17 26 13 19 10 10 39 33 40 39 25 40 21 30 15 15 Max Unit Ui MHz ns ns ns ns ns ns CL = 5.0 pF CL = 45 pF, F RL = 667 CL = 15 pF F Test C di i T Conditions
AC SETUP REQUIREMENTS (TA = 25C, VCC = 5.0 V)
Limits Symbol S bl tW tW tW ts ts th th trec Parameter P Clock Pulse Width HIGH Clock Pulse Width LOW Clear Pulse Width LOW Data Setup Time Select Setup Time Data Hold Time Select Hold Time Recovery Time Min 25 13 20 20 35 0 10 20 Typ Max Unit Ui ns ns ns ns ns ns ns ns VCC = 5 0 V 5.0 Test C di i T Conditions
FAST AND LS TTL DATA 5-4
SN54/74LS299
3-STATE WAVEFORMS
VIN
1.3 V tPLH
1.3 V tPHL 1.3 V
VIN
1.3 V tPLH
1.3 V tPHL 1.3 V
VOUT
1.3 V
VOUT
1.3 V
Figure 1
Figure 2
VE 1.5 V VE VOUT tPZL 1.5 V 0.5 V 1.5 V tPLZ 1.5 V VOL
VE 1.5 V VE tPZH 1.5 V VOUT tPHZ 1.5 V VOH 1.5 V 0.5 V
Figure 3
Figure 4
AC LOAD CIRCUIT
VCC RL SW1 tPZH tPZL TO OUTPUT UNDER TEST tPLZ tPHZ
SWITCH POSITIONS
SYMBOL SW1 Open Closed Closed Closed SW2 Closed Open Closed Closed
5 k CL* SW2
* Includes Jig and Probe Capacitance.
Figure 5
FAST AND LS TTL DATA 5-5

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